In a digital transmission system the basic signal is made up by first-order multiplexing at a rate of 2.048 M bit/s, corresponding to a capacity of 30 telephone channels. At equipment junctions this signal is transmitted by electric cables by means of high-density bipolar code designated HDB.sub.3 and standardized by the CCITT.
The HDB.sub.3 code is a special form of the HDBn code, which is a three-level (-,0,+) bipolar code in which:
the binary ones are represented by rectangular pulses having a duty factor of 1/2, alternatively positive or negative, PA1 the binary zeros are represented by vacant time intervals except when they follow one another and are greater than n, in which case every sequence of n+1 successive zeros is replaced by a packing sequence of n+1 elements in which all the elements are zeros with the exception of the first and the last, the last element being an exception to the bipolarity rule, that is a pulse of duty factor 1/2 of the same polarity as the one which preceeded it, the first element being either a zero or a normal bipolar one, the choice being made in such a way that the polarity of an exception is different from that of the last previous exception. PA1 the binary ones are represented alternatively either by a rectangular pulse of duty factor 1 or by a vacant time interval PA1 and the binary zeros are represented by a rectangular pulse of duty factor 1/2 occurring in the first half of a time interval or, according to a variant, in the second half of a time interval. PA1 expressing each binary digit of an initial value as a signal element having alternatively either an initial level or a second level, both maintained throughout the entire binary interval; PA1 expressing each binary digit of a second value not belonging to a sequence of n+1 successive digits of the second value, as a signal element of the first level maintained during the first half of the binary interval and followed by a signal element of the second level maintained during the second half of the binary interval; PA1 and expressing binary digits of a sequence of n+1 successive digits of the second value in accordance with the above rule, with the exception of the first and the last, the first being expressed in accordance with the above rule as a digit of the second value except in the case where the binary digits of the first value appeared after the preceeding sequence of n+1 successive binary digits of the second value and are an even number, in this case it is expressed as a binary digit of the first value, the last being expressed as a binary digit of the first value contradicting the rule of alternation. PA1 a discriminator placed at the input, which separates the input signal pulses in relation to their polarity and restores them under a single polarity at two separate outputs, one reserved for pulses of positive origin, the other for pulses of negative origin, PA1 a double shaping circuit connected to the outputs of the discriminator which, under the action of a clock signal synchronized with the binary intervals of the input signal, expands the pulses appearing at the discriminator outputs, gives them a duty factor of 1/1 before passing them to two separate outputs, one reserved for pulses of positive origin, the other for originally negative pulses, PA1 a gating circuit connected to the outputs of the double shaping circuit which, under the action of the clock signal, delivers pulses of duty factor 1/2 in the absence of pulses at the outputs of the double shaping circuit, PA1 and an adder connected to the output of the gating circuit and to that of the double shaping circuit delivering pulses of positive origin, which supplies the output signal for the encoder. PA1 a clock regeneration circuit delivering an inverted clock signal whose period corresponds to one binary interval of the input signal and whose trailing edges coincide with the leading edges of the input signal, PA1 a logic "and" gate with two inputs, one fed with the decoder's input signal and the other the regenerated and inverted clock signal, PA1 a logic "nor" gate with two inputs which are connected in parallel with those of the "and" gate, PA1 a delay circuit connected to the output of the "nor" gate which, under the action of the regenerated and inverted clock signal, delays the pulses available at the output of the "nor" gate by a half binary interval, PA1 and a differential-input amplifier with one input connected to the output of the logic "and" gate and the other connected to that of the "nor" gate, the said amplifier delivering the output signal of the decoder. PA1 a clock regeneration signal delivering a regenerated clock signal defining the binary intervals associated with data units contained in the signal to be regenerated, PA1 a delay circuit with its input fed with the regenerated clock signal and delivering a version of the regenerated clock signal, delayed by a period less than a half binary interval, and at a multiple close to the binary interval, PA1 a sampling circuit fed with the signal to be regenerated at one sampling input and with the regenerated and inverted versions of the clock signal at its sampling control inputs, ensuring brief sampling during the first half of each binary interval following a transition of the delayed version of the regenerated clock signal, PA1 a second sampling circuit with one sampling input fed with a complementary version of the signal to be regenerated and its sampling control inputs fed with the regenerated and delayed versions of the clock signal, ensuring brief sampling of the first and second halves of each binary interval following transitions of the delayed version of the regenerated clock signal, PA1 and a bistable flip-flop having a reset-to-1 input connected to the output of the first sampling circuit and a reset-to-zero input connected to the output of the second sampling circuit and delivering the regenerated signal. PA1 a clock regeneration circuit delivering an inverted clock signal whose period corresponds to one binary interval of the input signal and whose leading edges coincide with the trailing edges of the input signal, PA1 a logic "and" gate with two inputs, one fed with the error detector input signal and the other with the regenerated and inverted clock signal, PA1 a logic "nor" gate with two inputs which are connected in parallel with those of the "and" gate, PA1 a delay circuit connected to the output of the "nor" gate which, under the action of the regenerated and inverted clock signal, delays the pulses available at the output of the "nor" gate by a half binary interval, PA1 a frequency doubler connected to the output of the clock regeneration circuit, PA1 a bidirectional shift-register with four stages A, B, C and D, having a clock input connected to the output of the frequency doubler, parallel data inputs for stages A and B and a serial data input for right shift, set to logic level 1, parallel data inputs for stages C, D and a serial data input for left shift, set to logic level 0, a right shift control input activated by the output signal of the "and" gate and a left shift control input activated by the output signal of the delay circuit, PA1 and a logic circuit detecting left and right overflow in the shift-register as well as double shift in the same direction within the latter, and responding by emitting at the output of the error detector an error signal which is also to reset the shift-register to its initial state.
A digital signal encoded in HDBn has redundancy: a maximum of n+1 vacant time intervals and alternate polarity exceptions which enable the cadence to be restored and the D.C. component to be eliminated and which, moreover, enable certain line errors to be detected.
Current fibre optic transmission systems use light sources with on-off modulation which do not allow bipolar codes to be used--only binary codes. Of these, the most frequently used is the CMI code (coded mark inversion) in which:
In the present systems, transcoding with intermediate decoding is carried out at the transition between a standard junction encoded in HDB.sub.3 and a fibre optic link encoded in CMI. This has a disadvantage in that it does not allow errors affecting the signal ancoded in HDB.sub.3 at the transmission junction to be checked at the receiving end because the data due to the HDB.sub.3 code redundancy is lost in the intermediate decoding used during HDB.sub.3 --CMI transcoding at the start of the fibre optic link. In fact, a long series of zeros or non-alternating polarity exceptions affecting the signal encoded in HDB.sub.3 at the transmission junction disappear during the HDB.sub.3 =CMI and CMI-HDB.sub.3 transcoding.
The object of the present invention is to avoid the aforesaid disadvantage by way of binary coding for optical fibre transmissions which, in the case of a link between two junctions standardized in HDBn, as regards reception, enables a signal encoded in HDB.sub.3 to be restored which is completely identical to that at the transmission junction.